1. Field of the Invention
The present invention relates to a method and an apparatus for inspecting a wafer. More particularly, the present invention relates to a method for inspecting a wafer for electrical defects of a semiconductor device formed on the wafer using electron beams and an apparatus for performing the same.
2. Description of the Related Art
Generally, semiconductor devices are fabricated by performing a series of unit processes to a wafer. When the unit processes for manufacturing the semiconductor devices are performed, defects that cause failures of the semiconductor devices can be generated on a wafer. These defect are generally divided into physical defects, like contaminant particles, and electrical defects, which cause faulty operation or electrical deterioration of the semiconductor devices. For example, electrical defects can include problems such as a contact that is not opened or a contact with an increased resistance.
Wafers are usually analyzed with electron beams to find electrical defects. In a method for analyzing wafers for electrical defects using electron beams, the electron beams are primarily irradiated onto a surface of a predetermined inspection region of a wafer. The surface of the wafer is charged instantly, and secondary electrons are then emitted from the wafer surface. The secondary electrons are detected and electrical defects on the wafer can then be analyzed by contrasting the voltages of the secondary electrons.
U.S. Pat. No. 6,091,249 (issued to Talbot et al.) discloses a method for analyzing a defect of a wafer using electron beams. According to the disclosure in U.S. Pat. No. 6,091,249, the process for analyzing wafers for defects is performed by instantly charging a pre-determined surface of a region of the wafer. However, when the surface of the wafer has been charged insufficiently, a sufficient voltage contrast generated from a defective region may not be obtained. As a result, an electrical defect generated on the surface of the wafer may not be detected.
After the analysis of the first region of the surface of the wafer is finished, another region of the wafer surface is then analyzed. When this second region of the wafer is adjacent to the first analyzed region of the wafer, which is common for ease of analysis, a section of the second region can overlap the first region. Because the first region has already been inspected and now has a charge, the overlapping section in the second region will have different charge characteristics from the rest of the second region. These different conditions can interfere with the detection process in the second region. This in turn can reduce the detection sensitivity and detection reliability of the testing apparatus.